Embedding a nonvolatile memory cell and a logic semiconductor device together on the same silicon substrate allows obtaining a high-performance semiconductor device. These semiconductor devices are widely used for industrial machines, household appliances, devices mounted on vehicles, and the like as an incorporated type microcomputer. Generally, a program needed for the microcomputer is stored in the nonvolatile memory embedded together, and is read for use as necessary.
In nonvolatile memory cells in practical use today, field effect transistors for storage are used, in which a threshold voltage varies with accumulation of an electric charge. The electric charge holding system of the field effect transistor for storage includes the floating gate system (refer to Japanese Patent Application Laid-Open Publication No. H05-121700 (Patent Document 1), for example) that stores an electric charge in a conductive material electrically isolated, and the MONOS system (refer to Japanese Patent Application Laid-Open Publication No. H05-048113 (Patent Document 2), for example) that stores electric charges in an insulator, such as a silicon nitride film, with a property to accumulate an electric charge.
The floating gate system has good characteristics for holding an electric charge, and widely used for flash memories for storing programs in cellular phones and large capacity flash memories for storing data, etc. However, maintenance of the capacitive coupling ratio needed for the potential control of the floating gate is increasingly complex with finer design rules, and memory cell structures are becoming more complicated. In addition, the thickness of an oxide film surrounding the floating gate must be 8 nm or more to control the leakage of a holding electric charge, the limit of the finer design rules aiming at high speed and high integration is approaching. Since the electric charge is stored in the conductive material, a single defect that could be a leakage path in the oxide film around the floating gate extremely shorten a period for holding an electric charge.
On the other hand, the MONOS system generally has poor characteristics for holding an electric charge than the floating gate system, and the threshold voltage tends to drop logarithmically with time. Therefore, although the MONOS system has been known for many years, only a small portion of products has used the system in practical use. However, since the MONOS system uses a discrete storage system that stores the electric charge in the insulator, existence of some leakage paths does not cause all the holding electric charge to be lost, and the MONOS system is advantageously tolerant to a defect of an oxide film surrounding the insulator. Therefore, the MONOS system has been paid attention to in recent years with the advancement of finer design rules. Since a thin oxide film of 8 nm or less can be applied, the system is suitable for finer design rules, reliability can be easily estimated since the time for holding an electric charge is not extremely shortened by a defect that happens with low probability, and the memory cell structure is simple and the system can be easily embedded together with a logic circuit section.
The simplest memory cell with the MONOS system includes the NROM structure (refer to U.S. Pat. No. 5,768,192 (Patent Document 3), and Japanese Patent Application Laid-Open Publication No. 2004-186452 (Patent Document 4), for example). This structure replaces the gate insulating film of the field effect transistor with the ONO film structure comprising an oxide film/nitride film/oxide film, and the CHE (Channel Hot Electron) system is used for writing, and the BTBT (Band-To-Band Tunneling) system with the interband tunneling is used for erasing. Simple formation processes thereof makes the system suitable for finer design rules and embedding together with the logic circuit section.
Another memory cell suitable for embedding together with a logic circuit section includes a split-gate type memory cell comprising a field effect transistor for selection, and a field effect transistor for a memory. This memory cell is suitable for embedding together because a faster writing operation and a smaller power supply can be provided with the SSI (Source Side Injection) system having good injection efficiency, and because the area of a peripheral circuit can be reduced since the transistor that selects this memory cell and the transistor connected thereto can be constituted with a transistor of a low voltage system with a small device area.
A split-gate type memory cell especially suitable for finer design rules includes a memory cell with a structure that forms one of the field effect transistors with a sidewall using self aligning (refer to Japanese Patent Application Laid-Open Publication No. H05-121700 (Patent Document 1), for example). In this case, since the alignment margin for photolithography is unnecessary, and the gate length of the field effect transistor formed with self aligning can be equal to or smaller than the minimum resolution dimension of the photolithography, a memory cell with design rules finer than a conventional memory cell in which the field effect transistor for selection and the field effect transistor for the memory are respectively formed with a photomask can be achieved.